Nonvolatile memory devices include a memory array containing a plurality of memory cells, addressing, and programming circuits. Included in the memory device are memory data registers which are generally used to store and retrieve data information stored in a memory cell. A data register can be used to store information that is to be written into a memory cell and may also be used to retrieve and store the information from a memory cell. An internal verify function within the data register includes the ability to verify, at a bit level, the expected polarity or data value stored in a memory cell and to communicate the verification status to a memory controller. Data registers are essential building blocks present in modern semiconductor memories, such as high-density flash memory devices, providing efficient programming and erase functions to verify the data to be stored in the memory cells.
Referring to FIG. 1, a memory array 10, within a memory device, has a plurality of storage or memory cells (not shown) and is coupled to a bit line (BL) select circuit 12. The bit line select circuit 12 selects a bit-line coupled to a memory array 10 of memory cells. In conjunction with a word line selection circuit (not shown), a memory cell is selected and coupled to a sense and program circuit 14. Generally, a selected memory cell is programmed to store an associated data value. During a program operation, data values are loaded into a page data register 16. For example, 512 or 1024 data values may be loaded into the data register 16. A selected memory cell is associated with a single data value in the data register 16. Next, a read operation is performed to determine whether the data value stored in the selected memory cell is correctly programmed.
A latch and verify circuit 17 stores the data value read from the memory cell. A comparison between the data value stored in the selected memory cell and the associated data value in the data register 16 is performed. If the data value read from the selected memory cell and the data value stored in the data register 16 match, then the data value programmed in the selected memory cell is verified, and the programming operation for the selected memory cell ends. If the data value read from the selected memory cell and the associated data value stored in the data register 16 do not match, additional programming steps must be performed on the selected memory cell. Iterative programming steps continue until all of the selected memory cells associated with a page of data values in the data register 16 have been verified.
A direct memory access (DMA) decoding block 18 may be included within a memory device to facilitate testing operations of the memory device. External pads an the memory device integrated circuit are used to access specific bit lines during probe and test operations. Examples of operations performed during a test operation include: applying predetermined voltages to specific memory cells, measuring leakage current, measuring operating currents, and measuring a variety of memory cell characteristics.
Conventional DMA circuitry requires decoding circuitry 19 for selecting a specific bitline. In FIG. 1, the NOR gate 3 represents the final stage of this DMA decoding circuitry 19. In the DMA circuit, the DMA decoding block 18 and the DMA select device 4 selectively couple a selected bit line to a global DMA access line 5. The global DMA access line 5 may be coupled to a pad on the memory device integrated circuit to directly access bit line information from the memory array 10 during a probe or testing operation. It is desirable to use as few devices as possible in the verify circuit 17, and in the DMA decoding circuitry 19. Since, a DMA circuitry 19 is associated with each data value stored in the data register 16, reducing the number of transistors in the DMA decoding circuitry 19 may provide a substantial savings in the layout of the memory device.